Clock

The clock synchronizes the different actions in the processor.

Throughout our processor, we've got latches / memory chips which are edge-triggered, and ones that are level-triggered. Edge-triggered chips usually trigger upon the rising edge of the clock, whereas level-triggered chips usually store their input while the clock is low.

By negating the clock, we can create two clock domains. A clock domain refers to a set of chips that are synchronized by the same clock such that they all store their inputs at (up to a delta of a few nanoseconds) exactly the same time. In fact, we have three clock domains:

• The “normal” clock. This is used in the ALU, for IO devices which synchronize with the CPU, and in some places in the control unit.
• The “inverted” clock. Since control lines need to be stable on rising edge, they need to change on falling edge. Thus, the control µISA runs on an inverted clock cycle. This clock is also used for the address latch post-increment mechanism.
• The “delayed” clock (generated on the Registers/Memory decoader board). The registers and the address latch are level-triggered. This is a problem since they start accepting data immediately once the clock gets low, even before control lines have started to stabilize. Thus, the clock controlling their input must not get low until several nanoseconds after the system clock has gotten low. However, it needs to get high immediately with the rising clock edge. This is realized by feeding ~CLK through a delay circuit using two schmitt inverters (74-14) and (N)ANDing it with ~CLK. This clock is used for the registers (except the accu), the address latch and the RAM memory.

The CPU can operate and pass a test suite at clock speeds of up to 2 MHz.

The clock module allows switching between manual and automatic clock modes. The manual mode can be advanced by pressing (and releasing) a button. The automatic mode works using a 555 timer in astable mode. Both the switch and the button are debounced. The clock can also be halted by the halt instruction until an interrupt arrives, or the clock is pulsed manually by pressing the step button. A combination of microarchitectural conditions (halt, interrupt and I/O state, manual mode) decides whether the timer automatically continues execution.

If the clock is stopped, we can always manually force the clock to get low and high again (which is one cycle) by pressing and releasing a button. Since the 555 timer continuously generates a clock signal, we need to make sure that stopping and starting the processor clock is synchronized with the clock signal. Otherwise, the processor clock could be, for example, enabled at the end of the low phase, which would create a cycle with a very short low phase. This might not give the control lines enough time to stabilize and lead to errors. Using a D flip-flop which is triggered by the inverted clock signal of the 555 timer, the processor clock is started and stopped only at the falling edge.

A clock cycle looks as follows:

• The clock edge falls. This changes the latches controlling the microcode address, and thus the control lines start changing. The delayed clock remains high
• The control lines stabilize. This happens during the first ~70 ns after the falling edge.
• The delayed clock also changes. The registers now start accepting inputs. Since they are level-triggered, they will simply continue to adopt new data until the clock changes again.
• The clock edge rises. Edge-triggered latches store their current inputs. Level-triggered inputs also stop storing now, which means that their last stored input is the one that was present in the instant before the clock change.
• The clock edge falls again. The cycle repeats. One thing we did not mention earlier was that on the falling edge, the address latch also increments or decrements. This ensures that the address latch increments after everything has happened, right before the control lines start fluctuating, but after a read from the contained address into the opcode register has happened. This seems cyclic, and actually is, but in practice there are several propagation delays between these changes which ensures that this works as intended.

Since we need a bit more time while the clock is low than while it is high, we configured the 555 timer to generate an asymmetric clock signal. This means that the normal clock has a duty cycle greater than 50 %. But because the 555 can only be configured in such a way that the duty cycle is smaller or equal to 50 %, the normal clock is actually the inverted clock signal of the 555.

LEDs used in the build

• The blue LED visualizes the CLK.
• The green LED next to the power supply visualizes RESET.
• The upper red LED visualizes HLT.
• The lower red LED visualizes whether automatic clock ticking is enabled.
• The yellow LED shows the sign bit of the immediate—or more precisely the value of DBUS7 when MEM_TO_DBUS is active.