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Timer

State of the part

This part is fully built and tested. We are currently working on integration testing.
Participators: Ferdinand, Johannes K., Julian D., Mona

Our implementations consists of two timers that can be separately addressed and set, and can count up to __ respectively.

In the construction we have two separate registers and comparators for two configurable timer intervals.
We also included a multiplexer in front of the clock input to choose between the FPGA clock or another clock signal which could be used to handle real time events.
The timers are identified by the D0 and D1 pins respectively, and reset by pulling down Q6 of the 377 chip.

We also use the timer for delays and the timing of the soundcard.

Schematics​

timer_-_multi_clock.svg

Layout​

timer_fritzing.svg

Addressing​

  • 0x0100: Configuration register
    • 0&1 clock divider
    • 5 clock selector
    • 6 reset (active low)
    • 7 count enable (active low)
  • 0x0120: Timer 2 compare register
  • 0x0140: Timer 1 compare register

Testing​

We used an Arduino Mega to simulate the address and data bus. It allows to set each of the two timers and count the clock cycles to check whether an interrupt is correctly triggered. Code can be found here in the io-main branch. TODO: if merged covert link to main

Interaction with Soundcard​

Since the timer can be chosen to run off the Clock given by our FPGA we can easily schedule our interrupts to load the next sample. This allows the MIDI Scheduling to be independent of the system clock and reduces the conversions needed to switch between our different time representations. As a side effect the consistent timing guarantees given by the soundcard clock allows for pseudo real time timers for other use cases which are invariant to system clock.

Findings​

  • Triggering too many interrupts could decrease overall CPU responsiveness. We fixed this by using the clock divider.
  • Timer can be used in software for lots of different purposes